This invention relates to semiconductor manufacturing processes, and more particularly to processes for gap filling between adjacent surfaces or levels of a semiconductor.
Many obstacles exist to further miniaturization of semiconductor components. Among these obstacles include the filling of metal interconnect layers to insure proper operation of the devices. Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias that are formed in an insulating layer. It is desirable to completely fill the via with the metal that is used to form the interconnect layer so as to insure optimal operation of the device.
For reasons of its cost, physical properties and availability, aluminum is presently the metal of choice for the fabrication of metal interconnect lines in integrated circuits. The interconnect lines are typically formed by a sputtering process which can result in less than optimal filling of the contact vias. Problems arise from the accumulation of relatively large grains of aluminum at the upper surface of the insulating layer. The accumulation of such grains at the edges of the contact via can block or otherwise obstruct the via prior to passage of the aluminum in sufficient quantity to completely fill the via, resulting in the formation of voids and uneven structures within the via. This problem is particularly acute as integrated circuits are fabricated using smaller geometries. The smaller contacts that are used in smaller geometry devices, such as the current 0.5 xcexcm and future generations of scaled technologies, necessarily have a larger aspect ratio (i.e., relationship of feature height to width) than do larger geometry devices, thereby exacerbating the via filling difficulties described above. For example, unduly large voids can result in contact resistance that is appreciably higher than designed. In addition, thinner regions of the aluminum layer adjacent to the via fill region will be subject to eletromigration, which can result in the eventual opening of the circuits and failure of the device.
A number of different approaches have been attempted to ensure optimal metal contact at lower interconnect levels. For example, refractory to metal layers have been used in conjunction with an aluminum interconnect layer to improve conduction throughout a via. In addition, via side walls have been sloped so as to improve metal step coverage into vias. The use of sloped side walls, however, has become less desirable as the industry adopts smaller device geometries. Even with the geometries above 0.5 xcexcm, the foregoing techniques have not completely overcome the difficulties in the via filling. It is believed that the problem of via filling in the past has been at least partially attributable to the relatively low temperatures at which the aluminum was processed incident to via filling. These temperatures typically are below 500xc2x0 C. which some manufacturers believe contributes to the formation of aluminum grain sizes that are unduly large for via filling.
U.S. Pat. No. 5,108,951 to Chen, et al., which issued on Apr. 28, 1992 attempts to address the foregoing problem of via filling arising from the flow of aluminum grains of unduly large size. In this patent, the temperature of the integrated circuit is heated to a temperature of about 400xc2x0 C. prior to the commencement of aluminum deposition. Aluminum is deposited into the via during the course of wafer heating to a temperature of about 500xc2x0 C. Aluminum is deposited into the via at a rate of about 30-80 xc3x85/sec during the course of wafer heating. This prior art system shares many of the same disadvantages of the previously addressed prior art, namely incomplete via filling, particularly at smaller via geometries. In addition, via filling is undertaken at temperatures in the vicinity of about 500xc2x0 C., which prevents the use of polymeric materials as dielectrics in the integrated circuit, as these polymeric materials typically decompose at such high temperatures.
In view of the foregoing deficiencies in the prior art, it is desirable to provide an integrated circuit filling process for contacts and vias which provides for a reliable filling at relatively low temperatures, preferably on the order of about 250-450xc2x0 C. Contact and via filling at such low temperatures will permit for the use of more optimal dielectric materials which is critical to the development of sub-0.5 xcexcm technologies.
As a consequence of the foregoing prior art deficiencies, it is desirable to provide a process for the filling of integrated circuit contacts and vias which is operable at relatively low temperatures of no more than about 300xc2x0 C., and preferably between about 20xc2x0-275xc2x0 C., which temperature range will permit for the use of low dielectric constant (xcexa) polymers (i.e., xcexa less than xcx9c3.0), the use of which has heretofore not been possible due to the high temperatures required in prior art via filling processes.
The invention provides a filled cavity structure, such as a contact or via, and process of cavity structure fill that can provides for a cavity fill at heretofore unprecedented low temperatures. The structure and process of the invention permit cavity filling with aluminum, aluminum alloys, copper, and copper alloys. Contacts and vias to be filled with such metals can optionally be lined with physical vapor deposition (xe2x80x9cPVDxe2x80x9d) or chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) refractory metals and/or metal alloys prior to deposition of the cavity fill material to enhance deposition of the fill metal within the cavity. The cavities to be filled can be formed through various dielectrics or combinations of dielectrics which exhibit advantageously low dielectric constants (xcexa) of less than about 3.0, and preferably between 1.5-2.5 or lower.
In accordance with the present invention, an improved filling process is provided which allows for enhanced filling of contacts, vias and trenches formed in dielectrics of integrated circuits, particularly sub-0.5 xcexcm technologies. In a preferred aspect of the invention, cavity filling proceeds in a multi-step process by first depositing a CVD or PVD liner or barrier layer, preferably at a temperature range of about 100xc2x0-300xc2x0 C. at sub-atmospheric processing pressures of about 0.1-50 Torr (1 atmosphere=760 Torr). Preferably, the liner is an elemental Ti-free liner of the type disclosed in U.S. Pat. No. 5,849,367 of G. Dixit, et al.
Once the liner/barrier layer has been deposited, elemental or pure aluminum can be CVD deposited at a temperature of xcx9c100xc2x0-300xc2x0 C. and processing pressure of about 0.1-50 Torr in a suitable cavity fill precursor atmosphere, such as dimethyl aluminum hydride (xe2x80x9cDMAHxe2x80x9d) or tri-isobutyl aluminum (xe2x80x9cTIDAxe2x80x9d), to a thickness of xcx9c500-5,000 xc3x85, followed (optionally) by an PVD aluminum alloy overlayer of Alxe2x80x94Cu(xcx9c0-2%), Alxe2x80x94Si(xcx9c1%)xe2x80x94Cu(xcx9c0.5-2%), Alxe2x80x94Ta(xcx9c0.01-0.5%), or Alxe2x80x94Ti(xcx9c0.01-0.5%). The composite aluminum/aluminum alloy stack is exposed to a pressure of about 1 atm.xe2x88x92xcx9c30 MPa at a temperature in the range of about 20xc2x0-300xc2x0 C. to completely fill the cavity by xe2x80x9cforce fillxe2x80x9d. Such processing is in sharp contrast to that of the prior art, which typically provides for processing at pressures in excess of 100-300 MPa and at temperatures typically in excess of 300xc2x0 C., and typically in excess of 450xc2x0-500xc2x0 C., which temperatures far exceed the decomposition temperature of polymeric dielectrics having dielectric constants below 3.0. The process of the present invention is applicable for a variety of metals and metal alloys, adjustments to the processing parameters disclosed above being undertaken in accordance with the various physical and chemical properties of the material to be filled into the respective cavities, gaps, holes or trenches.
Suitable metals and metal alloys for use in the present invention include, by way of non-limiting example, the following materials: (1) Alxe2x80x94Ti (0.1%)xe2x80x94Cu(0.5%); (2) Alxe2x80x94Cu (0.5%); (3) Alxe2x80x94Cu (1%); (4) Alxe2x80x94Si (1%)xe2x80x94Cu (0.5%); and (5) aluminum. In addition, the process of the present invention is suitable for use with refractory metals and metal alloys, such as. (1) copper (Cu): (2) alloys of copper with one or more of magnesium (Mg), gold (Au) and silver (Ag); and Alxe2x80x94Scxe2x80x94Cu. The process of the invention is also applicable for use in the application of various refractory claddings and bassiers, such as those formed from titanium (Ti), TiN, combinations of Ti and TiN, TiW, and tungsten (W).
The processing regimen of the present invention is particularly advantageous when processing integrated circuits with polymeric insulators since such insulators typically decompose at temperatures of about 350xc2x0 C. or greater. Such polymeric insulators include, by way of non-limiting example, the family of polytetrafluoroethylene (xe2x80x9cPTFExe2x80x9d) compounds, which exhibit a dielectric constant of 1.9 and are therefore very attractive because of their ability to reduce parasitic capacitance of interconnects, parylene, aerogels and xerogels.
The processing techniques of the present invention are also applicable to ensure complete filling of holes and/or trenches that are formed through various dielectic materials or combinations of dialectic materials. As such the process techniques of the present invention are applicable for the family of damascene and dual damascene processing techniques, in which a groove is etched or otherwise formed in an oxide or other dielectric, then filled with a metal (usually tunsten or copper) in an appropriate deposition process such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d), after which the applied metal is polished so as to be flush to the surface of the dielectric. In the dual damascene process, not only is a groove etched or otherwise formed in the dielectric, but in addition thereto a via is patterned and etched so as to extend from an upper level of metal through a dielectric to a lower level of metal. Suitable dielectrics for use in the present invention include the family of polymeric spin-on-glass (xe2x80x9cSOGxe2x80x9d) materials, such as the 1500 Series manufactured by Allied Signal Corp.; the family of PTFE; parylene; polyimides; hydrogen silsesquioxane; aerogels and surface modified aerogels such as fluorinated and methylated aerogels, all of which are more fully described an incorporated herein by reference in one or more of the following copending patent applications: (1) Ser. No. 08/234,100 filed Apr. 28, 1994 and entitled xe2x80x9cSelf-Aligned Via Using Low Permittivity Dielectricxe2x80x9d; (2) Ser. No. 08/286,761 filed Aug. 5, 1994 entitled xe2x80x9cPorous Dielectric Layer With a Passivation Layer for Electronics Applicationsxe2x80x9d; (3) Ser. No. 08/294,290 filed Aug. 23, 1994 entitled xe2x80x9cSelf-Aligned Contact Using Organic Dielectric Materialsxe2x80x9d; (4) Ser. No. 08/246,432 filed May 20, 1994 entitled xe2x80x9cInterconnect Structure with an Integrated Low Density Dielectricxe2x80x9d; and (5) Ser. No. 08/333,015 filed Nov. 1, 1994 entitled xe2x80x9cPillars For Improved Damascene Conductor Fabricationxe2x80x9d.